(1) Field of the Invention
The present invention relates generally to the field of integrated-circuit (IC) manufacturing process, and more particularly, to an improved fabrication process of interlayer dielectric underlayer.
(2) Description of the Prior Art
In order to form compact and high density devices, multiple layers of conductors and insulators are stacked within the limited area in IC fabrication. It tends to have steep and complicated topography on the wafer surfaces. The mentioned scenario can be more caustic in the process of dynamic random access memory (DRAM) because the alternating multi-layers of polysilicon and dielectric layers are deposited and etched to form the capacitors. These complicated topography on wafer surfaces has severe negative effect on subsequent processes. It will diminish the range of depth of focus during lithography exposure especially and distort the photoresist profiles or even cause residue during etching, and it may produce undesired metal lines shorting. The planarization technologies of so-called "biased sputter oxide deposition" or "oxide reflow" are currently employed to solve the topography problem, however they are both time consuming and costly. U.S. Pat. No. 5,393,708 to Hsia et al. (the entire disclosure of which is herein incorporated by reference) describes another simple and low cost technique which is used spin-on-glass (SOG) for planarization as the dielectric interlayer material between two metal layers. The conventional SOG process steps are as following:
By employing tetraethoxysilanes (TEOS) as reacting gas, a layer of SiO.sub.2 with the refraction index between 1.44 and 1.46 is deposited by the plasma enhanced chemical vapor deposition (PECVD) method, then deposited another dielectric SiO.sub.2 layer by using high density O.sub.3 /TEOS as reacting gas, following employ SOG planarization process to achieve the planarization of the mentioned interlayer dielectric. However the high sensitivity of O.sub.3 /TEOS surface causes a known problem in the art. The thickness of O.sub.3 /TEOS layer will be affected by the interaction between O.sub.3 /TEOS surface and that of PE-TEOS during the deposition of O.sub.3 /TEOS onto the PE-TEOS dielectric underlayer. Moreover it may result in a non-uniform thickness of dielectric layer because of the inhomogeneties in PE-TEOS layer. Besides, the various aspect ratios of metal lines of prior layer tend to prevent the deposition of SiO.sub.2 from filling into the gap between metal lines completely and degrade the planarization efficiency of the interlayer dielectric layer. Conventionally, there are several methods of improving the O.sub.3 /TEOS surface sensitivity problem include following techniques: (1) plasma or chemical treatment on wafer surface; (2) dual frequency PE-TEOS dielectric underlayer deposition; (3) low density O.sub.3 /TEOS layer is deposited prior to the deposition of high density O.sub.3 /TEOS interlayer dielectric. With these approaches, the process is more complicated and a simpler method is needed. This invention reveals an improved process of interlayer dielectric planarization, particularly for solving the O.sub.3 /TEOS surface sensitivity problem in the fabrication process of dielectric underlayer.